A Khepera add-on turret for evolutionary experiments in hardware on a single or a group of Khepera
robots using FPGA (Field Programmable Gate Arrays). It handles both "extrinsic" and "intrinsic"
evolution of functions, connections, and the physical characteristics of the cells of the FPGA. The
results of the artificial evolution are tested on Khepera. Khepera's on-board processor manages the
transfer of data to and from the FPGA. All features of the FPGA (cell functions and connections)
can be accessed by a user-defined genotype for exploitation by the evolutionary process. User defines the
selection and evaluation schemes, as well as the use of a pre-formatted genotype.
High performance FPGA XC6216 by Xilinx which has the following specifications, is used.
- 4096 cell arrangement in a 64 x 64 matrix format
- Each cell has some 40 logic and other functions
- Detailed structure, rich registers, and gates
- High speed SRAM control memory
- 220 MHz basic clock
- 16 bit input and 7 bit output are connected to Khepera through K-BUS
- Size of turret: 55 mm in diameter x 10 mm
Functions of Turret
A genotype used on the turret consists of genes each of which specifies either how a cell should be
connected with other cells or terminals, or how it should behave in the evolution experiments. It is
downloaded from a host computer to the FPGA on the turret with the help of Khepera's main processor
(MC68331). A gene consists of 3 bytes of information specifying the cell functions and connections
between the cell's neighbouring cells or the FPGA's input/output lines. All of a cell's 40 functions
can be selected, and all 3 modes of inter-cell connections (Fast LANEs, Length-4 Fast LANEs,
Length-16 Fast LANEs) in all 4 directions (north, south, east, and west) can be specified. The
genotypes, expressed as a string of bytes at the host and MC68331, are converted into a bit string
on XC6216 by hardware for fast loading. Output from the FPGA's 7 output lines are posted on
K-bus and read by MC68331. It can be processed by MC68331 or sent to the host for evaluation. In
the case of a smaller population, the entire set of genotypes, as well as the mechanism for managing
the process of artificial evolution, could be stored on-board Khepera, allowing a host free evolution.
Experiments Options - "Extrinsic" Evolution
Evolutionary computing takes place mostly "off-line" on the host computer. Once a new
generation of individuals is established by selection and sexual recombination, each genotype in the
population describes functions and connections of the cells of FPGA and other parameters that define
the running of the reconfigurable hardware. The new generation is then implemented, one genotype at
a time, on the FPGA with the help of Khepera's main processor (MC68331) and run. The resulting
behavior of the phenotype (combined behavior of Khepera and FPGA) is then evaluated by either
software on MC68331, the evaluation mechanism on the host, or by human observer(s). A set of new
genotypes is formed after the selection and sexual recombination, and the process continues.
Experiments Options - "Intrinsic" Evolution
In "intrinsic" hardware evolution, FPGA's physical characteristics are drawn into the
process of evolution to achieve desirable sensory-motor responses. The intrinsic evolution includes
extraction of electrical, electronic, and quantum electronic device characteristics of the FPGA that
are not even intended in the original design of FPGA and its cells. The genotype still dictates the
selections of cell functions and inter-cell connections. However, the purpose of evolution is not to
achieve over-all functions expected of such selected functions and connections of the cells that
comply with the nominal design of the FPGA. Rather, the objective is to extract from whatever
physical characteristics of the configured FPGA desirable input (sensor) - output (motor) signal
relationships that work towards achieving the fitness criteria. Much of the causes which are
responsible for the evolved signal relationships may not be readily explained as the evolutionary
process actively exploits "side-effects" and obscure physical phenomena of the VLSI to
improve fitness value. Again, Khepera's on-board processor (MC68331) mediates the transfer of
genetic information to and from the FPGA.
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